1. Field of the Invention
The present invention relates to a semiconductor circuit apparatus available to a scan test and to a scan test method for a semiconductor circuit.
2. Description of Related Art
With an increase in the number of transistors and other electronic components contained in a large-scale integrated circuit, which is abbreviated hereinafter as “LSI”, demand for more highly integrated and higher performance LSI is growing, and the number of macro cells such as memories and CPU integrated into the LSI is increasing accordingly. In order to improve the manufacturing quality of the LSI with a number of macro cells integrated thereto, it is necessary to maintain high test quality in the functional test of the LSI. A scan test having a high fault detection rate is therefore widely used. Further, a technique called a sequential scan has been introduced, which allows a connection test of a macro cell with surrounding circuits and a path delay test on a circuit including macro cells in the LSI.
The scan test is a technique that forms a shift register with a serial connection path connecting flip-flops inside an LSI, and directly controls and observes each flip-flop from outside. This shift register chain is called a scan chain. It allows dividing a logic circuit inside the LSI into several parts using the flip-flop in the LSI as an input or output point, and testing each part. This technique facilitates the generation of test patterns that increases exponentially with respect to the circuit scale.
The scan test process first performs shift operation to set the value of each flip-flop, which is called “scan shift”. It then input each flip-flop value to surrounding combinational circuits to activate the circuit, which is called “launch”. The value obtained by the launch is captured by the flip-flop at the end point of a path to be tested, which is called “capture”. Finally, the test process again performs the shift operation to the scan chain and outputs the result to the outside, thereby detecting faults inside the LSI. This cycle is repeated with various test patterns and exhaustively on various paths to be tested, thereby accomplishing the functional test of the logic circuit inside the LSI.
A conventional method of the scan test is as follows. In order to eliminate the need for setting an output value of a macro cell, a path bypassing the macro cell between the input terminal and the output terminal is formed. A selector is connected to the output terminal of the macro cell. During the scan test, the selector is controlled to select the bypass path, thereby conducting the scan test without activating the macro cell. This method is referred to hereinafter as a basic scan. This method requires the LSI to have a control terminal for controlling the selector from outside.
Japanese Unexamined Patent Application Publication No. 2001-42008 (Fujii et. al.) discloses a technique that places a path bypassing a macro cell in an LSI to separate the macro cell from other logic circuits and conducts the basic scan test only on the other logic circuits. Japanese Unexamined Patent Application Publication No. 11-83958 (Takahashi) discloses a test pattern generator for an LSI having a plurality of partial circuits. When testing a specific partial circuit, this technique directly gives input through a selector placed immediately before the specific partial circuit and directly obtains output through a selector placed immediately after the specific partial circuit, thereby conducting the scan test per divided partial circuits.
On the other hand, the sequential scan test aims to confirm the connection between a macro cell and a surrounding circuit and to detect a delay fault in a circuit including a macro cell. Thus, it is necessary to conduct the scan test without bypassing the macro cell, and the macro cell needs to operate to set output values. Hence, the sequential scan test has the problem of a heavy processing load on a test design tool such as Automatic Test Pattern Generator (ATPG) due to complexity in test pattern generation. Further, given recent trend of increasing number of macro cells incorporated into the circuit, there are cases where a plurality of macros exists on a logic path for which fault detection is to be performed. The processing load on a test design tool multiplies exponentially for the number of incorporated macro cells. It leads to an increase in the runtime of the test design tool and sometimes exceeds the processing capacity of the test design tool.
If the sequential scan having the above problem is conducted on the LSI disclosed by Fujii et.al., the bypass setting causes all macro cells to be bypassed, thus failing to conduct the sequential scan on the path including some of the macro cells. On the contrary, no bypass setting leads to activate all the macro cells included in a logic cone of a path to be tested and set the output values, resulting in an increase in a test pattern generation time and a test time. This fails to efficiently conduct the sequential scan that detects path delay faults in the path including the macro cell.
Further, Takahashi merely discloses the test pattern generator that divides an LSI to be tested into several partial circuits having a suitable circuit scale and generates a test pattern for each partial circuit to reduce the number of test patterns. The disclosed technique of dividing the circuit does not allow testing on the path beginning at a flip-flop in a partial circuit and ending at a flip-flop in another partial circuit. Thus, this technique is different in the test method from the scan test that connects flip-flops inside the LSI by a scan chain. It is therefore incapable of solving the problem of an increase in a test pattern generation time and a test time when conducting the sequential scan on a path including macro cells.
FIG. 5 is a block diagram showing a logic circuit of an LSI which is available to a conventional basic scan test. Macro cells 41 and 42 and flip-flops 511 to 519 operate in synchronization with one input clock. A scan chain is formed from an input terminal SCANIN through the flip-flops 511 to 519 to an output terminal SCANOUT. When conducting the scan test, the scan chain repeats the scan shift operation for each clock, thereby determining the values of the flip-flops 511 to 519. For example, in the configuration of FIG. 5, the scan shift operation of nine clocks in total determines the value of each flip-flop 511 to 519. Controlling the output value of each flip-flop by the scan shift operation allows each flip-flop to serve as a virtual input or output terminal. This enables testing of the LSI per a small logic cone composed only of combinational circuits that begins with a flip-flop and ends with another flip-flop. Combinational logic circuits 52 and 53 are activated by input of the set value of the flip-flop. The result value is latched by the flip-flop at the end of the logic cone in a next clock cycle. The shift operation by the scan chain is then repeated, thereby outputting the value captured by the flip-flop to the SCANOUT terminal. The value is compared with an expected value to detect a fault.
When conducting the basic scan test on the LSI of FIG. 5, selectors 43 and 44 are collectively set to select bypass paths 66 and 67 that bypass macro cells 41 and 42, respectively, by a signal from an input terminal BYPASS through a control line. Thus, setting the input terminals of the macro cells connected to the bypass paths to an expected value eliminates the need for activating the macro cells.
On the other hand, the sequential scan test requires setting the output value of the macro cells without bypassing them. Thus, to conduct the sequential scan test on the LSI of FIG. 5, it is necessary to collectively set the selectors 43 and 44 to select output paths from the macro cells by a signal from the input terminal BYPASS. Thus, when testing a path including the macro cell 41, for example, if the macro cell 42 is included in the logic cone of the path to be tested, it is required to activate not only the macro cell 41 but also the macro cell 42 to set the output values. This impedes an efficient sequential scan test.
The load on a test design tool when generating test patterns for the sequential scan test is described hereinafter with reference to the conceptual diagram of FIG. 6. FIG. 6 shows a macro cell 61 and logic cones ending at the input terminal DI of the macro cell 61. One of the illustrated logic cones is composed of combinational logic circuits 621 to 623 and begins at four flip-flops 611 to 614. In this case, setting four flip-flops by the scan shift allows setting one input terminal of the macro cell 61.
Generally, transition of the macro cell to a certain state requires setting a plurality of input terminals for the macro cell. If the number of input terminals is “n” and the number of flip-flops at the beginning of the logic cones that end at each input terminal is “A” on average, it is necessary to control the output of A*n number of flip-flops. The number of combinations of input patterns of all the flip-flops in this case is 2A*n. Thus, generating test patterns with the test design tool requires 2A*n number of combinations for one clock cycle operation of the macro cell. The number of combinations required when setting the value of the flip-flops to 0/1 indicates “complexity”, which is used as an index of difficulty in test pattern generation.
Moreover, since the output values of the macro cell cannot be determined in one clock cycle, the complexity further increases. For example, a RAM macro requires at least one clock cycle for writing data to an address and another one clock cycle for reading the data. A macro cell such as CPU requires several clock cycles from input of a command code to output of the result. Thus, if it is assumed that “m” number of internal state transitions are required to determine the output of the macro cell, since the complexity in one clock cycle operation of the macro cell is 2A*n, the entire complexity is m*2A*n. Further, since the sequential scan is expected to detect delay faults in the path beginning or ending at a macro cell, if another macro cell exists in the logic cone to be tested, it is necessary to control a plurality of macro cells at the same time. The complexity in this case is expressed as a power of the number of macro cells compared to the complexity when only one macro cell exists. For example, the complexity when using “k” number of macro cells is mk*2Ank.
In contrast, in the case of the basic scan that bypasses the macro cells, the complexity is as small as 2Ak since setting of only one input terminal of the macro cell is required. Thus, the sequential scan requires mk*2Ak(n-1) times of the processing by the test design tool compared to the basic scan. As described above, the present invention has recognized that the sequential scan for the LSI having a plurality of macro cells requires a heavy load on the test design tool and an extremely long processing time, which impedes the implementation of test design.